High level transistor transistor logic 高级晶体管晶体管逻辑电路
Static and Dynamic Performance of Micropower Transistor Logic Circuits 微功率晶体管逻辑电路的静态性能和动态性能
The base circuit cell of the de-cision circuit is source-coupled field-effect transistor logic ( SCFL) circuit. 判决电路的基本单元为源耦合场效应晶体管逻辑(SCFL)电路,时钟提取电路由预处理器和锁相环构成。
The basic DRAM cell is comprised of a transistor and a capacitor. The digit that is saved in the storage cell is determined as logic 1 or 0, by the voltage potential stored inside the capacitor. DRAM存储单元由一对MOS管-电容对组成,电容的电位决定了存储单元的逻辑是1还是0。
In chapter 4, the circuit of the carrier synchronization unit is implemented on FPGA, the Resistor Transistor Logic ( RTL) schemes are presented. 第四章在FPGA平台上实现载波同步单元电路,并给出了实现后的FPGA资源消耗、寄存器传输逻辑(RTL)原理图。
Based on the I-U characteristics of single-electron transistor ( SET) and the concepts of CMOS digital circuits design, a sort of logic gate is proposed. 基于单电子晶体管(SET)的I_U特性和CMOS数字电路设计思想,提出了一类互补型SET逻辑门。
In the brushless model, the IGBT ( Isolated Gate Bipolar Transistor) switch state period table is gained by GAL ( Generic Array Logic) which analyzes the signal of position feed-back. 在无刷直流方式下,用GAL对位置反馈信号进行逻辑综合,得到开关管的导通规律。
A Modified Schottky Transistor Logic Circuit with High Speed and Micropower Consumption 高速微功耗改进型肖特基晶体管逻辑
Three transistor dynamic cells and buffered I/ O control logic are used for the device. The control circuit is optimized for Y C separation system. 电路采用了三管动态存储单元和带缓冲的I/O单元,并针对Y-C分离算法的要求对控制电路进行优化。
The design of quaternary edge triggered JK type flip flop is proposed. The computer simulation and the test on experimental circuit composed of transistor transistor logic ( TTL) gates show that the flip flop has the predetermined logic function. 提出一种具有四轨输出的四值维持阻塞JK触发器的电路设计,经计算机模拟和测试由TTL门电路组成的实验电路表明,该触发器能实现预定的功能。
Traditional logic gate is composed of transistors, with transistor size will reach the limit, the bottleneck of the development of the traditional logic gates is coming soon. 传统逻辑门由晶体管构成,随着晶体管尺寸缩小即将达到极限,传统逻辑门面临的发展瓶颈。